`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/10 18:33:00
// Design Name: 
// Module Name: reg_WB
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module reg_WB(
    input wire clk,
    input wire rst_n,
    input wire [31:0] mem_data,
    input wire [31:0] alu_c,
    input wire [31:0] pc,
    input wire [1:0] WBSel,
    input wire [1:0] RegWEn,
    input wire [4:0] rd,
    output reg [31:0] data_back,
    output reg RegWEn_out,
    output reg [4:0] rd_out
    );
wire [31:0] pc_4;
assign pc_4 = pc + 32'd4;
   
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) data_back <= 32'b0;
    else begin
        case(WBSel)
        2'b00:data_back <= alu_c;
        2'b01:data_back <= mem_data;
        2'b10:data_back <= pc_4;
        default:data_back <= 32'b0;
        endcase 
     end
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) rd_out <= 5'b00000;
    else       rd_out <= rd;
end   

 always @(posedge clk or negedge rst_n) begin
    if(~rst_n) RegWEn_out <= 0;
    else       RegWEn_out <= RegWEn;
end

endmodule
